Discrete Dynamics Finite State Machines גרא וייס המחלקה למדעי המחשב אוניברסיטת בן-גוריון

Similar documents
Finite State Machines. CS 447 Wireless Embedded Systems

Cyber-Physical Systems Discrete Dynamics

Embedded Real-Time Systems

Embedded Systems 2. REVIEW: Actor models. A system is a function that accepts an input signal and yields an output signal.

Introduction to Embedded Systems

Embedded Systems 5. Synchronous Composition. Lee/Seshia Section 6.2

Embedded Systems Development

TRANSITION CONFLICTS DETECTION IN BINARY MODULAR STATECHART DIAGRAMS 1. Grzegorz Łabiak

Laurea Specialistica in Ingegneria. Ingegneria dell'automazione: Sistemi in Tempo Reale

Introduction to Embedded Systems

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI

Data Mining and Machine Learning

AI Principles, Semester 2, Week 2, Lecture 5 Propositional Logic and Predicate Logic

Continuous Dynamics Solving LTI state-space equations גרא וייס המחלקה למדעי המחשב אוניברסיטת בן-גוריון

Propositional logic (revision) & semantic entailment. p. 1/34

CS 2800: Logic and Computation Fall 2010 (Lecture 13)

The STATEMATE Semantics of Statecharts. Presentation by: John Finn October 5, by David Harel

Information System Design IT60105

{},{a},{a,c} {},{c} {c,d}

With Question/Answer Animations. Chapter 2

The Importance of Being Formal. Martin Henz. February 5, Propositional Logic

Model-Based Design. Chapter Modeling Physical Dynamics Newtonian Mechanics

INTRODUCTION TO LOGIC. Propositional Logic. Examples of syntactic claims

Advanced Topics in LP and FP

A Deterministic Logical Semantics for Esterel

Linear Temporal Logic and Büchi Automata

CHAPTER 10. Gentzen Style Proof Systems for Classical Logic

3. Only sequences that were formed by using finitely many applications of rules 1 and 2, are propositional formulas.

Symbolic Verification of Hybrid Systems: An Algebraic Approach

Part I: Definitions and Properties

A test sequence selection method for statecharts

Time-bounded computations

Stochastic Histories. Chapter Introduction

Logical Agents. Knowledge based agents. Knowledge based agents. Knowledge based agents. The Wumpus World. Knowledge Bases 10/20/14

Opus: University of Bath Online Publication Store

TECHNISCHE UNIVERSITEIT EINDHOVEN Faculteit Wiskunde en Informatica. Final exam Logic & Set Theory (2IT61) (correction model)

Chapter 4: Classical Propositional Semantics

Logic Model Checking

Mathematical Foundations of Logic and Functional Programming

State Machines Composition

Propositional Logic and Semantics

THE LANGUAGE OF FIRST-ORDER LOGIC (FOL) Sec2 Sec1(1-16)

Propositional and Predicate Logic - II

Automata-Theoretic Model Checking of Reactive Systems

CHAPTER 4 CLASSICAL PROPOSITIONAL SEMANTICS

Fuzzy Propositional Logic for the Knowledge Representation

Discrete Mathematics & Mathematical Reasoning Predicates, Quantifiers and Proof Techniques

An Introduction to Hybrid Systems Modeling

First Order Logic: Syntax and Semantics

Math From Scratch Lesson 29: Decimal Representation

Introduction to Metalogic

Numbers that are divisible by 2 are even. The above statement could also be written in other logically equivalent ways, such as:


Chapter Two: Finite Automata

COMP219: Artificial Intelligence. Lecture 19: Logic for KR

Propositional logic. First order logic. Alexander Clark. Autumn 2014

Theoretical Foundations of the UML Lecture 18: Statecharts Semantics (1)

INTRODUCTION TO PREDICATE LOGIC HUTH AND RYAN 2.1, 2.2, 2.4

ICS141: Discrete Mathematics for Computer Science I

COMP219: Artificial Intelligence. Lecture 19: Logic for KR

[read Chapter 2] [suggested exercises 2.2, 2.3, 2.4, 2.6] General-to-specific ordering over hypotheses

EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization

Failure Diagnosis of Discrete-Time Stochastic Systems subject to Temporal Logic Correctness Requirements

On the Complexity of the Reflected Logic of Proofs

Model Checking: An Introduction

Infinite Truth-Functional Logic

CHAPTER 1. MATHEMATICAL LOGIC 1.1 Fundamentals of Mathematical Logic

Lecture 12: Core State Machines II

cse541 LOGIC FOR COMPUTER SCIENCE

Bounded Retransmission in Event-B CSP: a Case Study

UNIT-I. Strings, Alphabets, Language and Operations

Propositional and Predicate Logic

Introducing Proof 1. hsn.uk.net. Contents

Lecture 05: High-Level Design with SysML. An Introduction to SysML. Where are we? What is a model? The Unified Modeling Language (UML)

Math 300 Introduction to Mathematical Reasoning Autumn 2017 Proof Templates 1

Chapter 11: Automated Proof Systems

Design of Embedded Systems: Models, Validation and Synthesis (EE 249) Lecture 9

A Sample State Machine

Synchronous circuits, Automata, Parallel composition

Logic for Computer Science - Week 2 The Syntax of Propositional Logic

Propositional Language - Semantics

Programming Languages and Types

Overview. Knowledge-Based Agents. Introduction. COMP219: Artificial Intelligence. Lecture 19: Logic for KR

Georg Frey ANALYSIS OF PETRI NET BASED CONTROL ALGORITHMS

Logic: Propositional Logic (Part I)

Equivalence of Regular Expressions and FSMs

CHAPTER 1: Functions

Notes on induction proofs and recursive definitions

Lecture 7. Logic. Section1: Statement Logic.

Linear Temporal Logic (LTL)

Discrete Mathematics. W. Ethan Duckworth. Fall 2017, Loyola University Maryland

Unit 1. Propositional Logic Reading do all quick-checks Propositional Logic: Ch. 2.intro, 2.2, 2.3, 2.4. Review 2.9

Knowledge representation DATA INFORMATION KNOWLEDGE WISDOM. Figure Relation ship between data, information knowledge and wisdom.

540 IEEE TRANSACTIONS ON AUTOMATIC CONTROL, VOL. 43, NO. 4, APRIL Algorithmic Analysis of Nonlinear Hybrid Systems

Logical reasoning - Can we formalise our thought processes?

198:538 Complexity of Computation Lecture 16 Rutgers University, Spring March 2007

Learning Goals of CS245 Logic and Computation

15414/614 Optional Lecture 1: Propositional Logic

Comparing State Machines: Equivalence and Refinement

Transcription:

Discrete Dynamics Finite State Machines גרא וייס המחלקה למדעי המחשב אוניברסיטת בן-גוריון

2 Recap: Actor Model An actor is a mapping of input signals to output signals S: R R k R R m where k is the number of input signals and m is the number of output signals u 1 u k S y 1 y m

3 Recap: Discrete Signals A signal e is discrete if there exists a one-to-one function f: t R: e t absent N that is order preserving, i.e., that t 1 t 2 f(t 1 ) f(t 2 ).

4 Example: Garage Counter Arrival Detector Departure Detector arrival Counter u up Σ i d down departure c count Display The counter actor has two input ports, up and down, both are pure signals. It has one output port, count, whose type is Z Formally: Counter i : absent, present R + {up, down} absent Z R +

5 State Space The state y(t) of the Integrator at time t is a real number. Hence, we say that the state space of the Integrator is States = R. For the Counter, the state s(t) at time t is an integer, so States Z. A practical parking garage has a finite and non-negative number M of spaces, so the state space for the Counter actor used in this way will be States = 0, 1, 2,, M. The state space for the Integrator is infinite (uncountable, in fact). The state space for the garage counter is finite. Discrete models with finite state spaces are called finite-state machines (FSMs). There are powerful analysis techniques available for such models, so we consider them next.

6 Finite State Machines If the number of states is reasonably small, then FSMs can be conveniently drawn using a graphical notation: guard / action State2 State1 Initial state indicator State3 Here, each state is represented by a bubble, so for this diagram, the set of states is given by States = {State1, State2, State3}. At the beginning of each sequence of reactions, there is an initial state, State1, indicated in the diagram by a dangling arrow into it.

7 Transitions Transitions between states govern the discrete dynamics of the state machine and the mapping of input valuations to output valuations. A transition is represented as an arrow going from one state to another. A transition may also start and end at the same state, as illustrated with State3 in the figure. In this case, the transition is called a self transition. State3

8 Guards and Actions The transition from State1 to State2 is labeled with guard / action. State1 guard / action State2 The guard specifies when the transition may be taken on a reaction. The action specifies what outputs are produced on each reaction. A guard is a predicate (a Boolean-valued expression) that evaluates to true when the transition should be taken, changing the state from that at the beginning of the transition to that at the end. When a guard evaluates to true we say that the transition is enabled. An action is an assignment of values (or absent) to the output ports. Any output port not mentioned in a transition that is taken is implicitly absent. If no action at all is given, then all outputs are implicitly absent.

9 Example: An FSM model for the garage counter Inputs: up, down pure Output: count {0,, M} up down / 1 up down / 2 up down / 3 up down / M 0 1 2 M down up / 0 down up / 1 down up / 2 down up / M 1

10 Example: An FSM model for the garage counter The inputs and outputs are shown using the notation name type. The set of states is States = {0,1,2,, M}. The transition from state 0 to 1 has a guard written as up down. This is a predicate that evaluates to true when up is present and down is absent. If at a reaction the current state is 0 and this guard evaluates to true, then the transition will be taken and the next state will be 1. Moreover, the action indicates that the output should be assigned the value1. The output port count is not explicitly named because there is only one output port, and hence there is no ambiguity. If the guard expression on the transition from 0 to 1 had been simply up, then this could evaluate to true when down is also present, which would incorrectly count cars when a car was arriving at the same time that another was departing.

11 Example If p 1 and p 2 are pure inputs to a discrete system, then the following are examples of valid guards: true p 1 p 1 p 1 p 2 p 1 p 2 p 1 p 2 Transition is always enabled Transition is enabled if p 1 is present Transition is enabled if p 1 is absent Transition is enabled if both p 1 and p 2 are present Transition is enabled if either p 1 or p 2 is present Transition is enabled if p 1 is present and p 2 is absent These are standard logical operators where present is taken as a synonym for true and absent as a synonym for false. The symbol represents logical negation. The operator is logical conjunction (logical AND), and is logical disjunction (logical OR).

12 Suppose that in addition the discrete system has a third input port p 3 with type V p3 = N. Then the following are examples of valid guards: p 3 Transition is enabled if p 3 is present (not absent) p 3 = 1 Transition is enabled if p 3 is present and has value 1 p 3 = 1 p 1 Transition is enabled if p 3 has value 1 and p 1 is present p 3 > 5 Transition is enabled if p 3 is present with value greater than 5

13 A model of a thermostat A major use of energy worldwide is in heating, ventilation, and air conditioning (HVAC) systems. Accurate models of temperature dynamics and temperature control systems can significantly improve energy conservation. Such modeling begins with a thermostat, which regulates temperature to maintain a set point, or target temperature. The word thermostat comes from Greek words for hot and to make stand. Consider a thermostat modeled by an FSM with States = {heating, cooling} Input: temperature R Output: heaton, heatoff pure temperature 18 / heaton cooling heating temperature 22 / heatoff

14 A model of a thermostat Suppose the set point is 20 degrees Celsius. If the heater is on, then the thermostat allows the temperature to rise past the set point to 22 degrees. If the heater is off, then it allows the temperature to drop past the set point to 18 degrees. This strategy is called hysteresis. It avoids chattering, where the heater would turn on and off rapidly when the temperature is close to the set point temperature. There is a single input temperature with type R and two pure outputs heaton and heatoff. These outputs will be present only when a change in the status of the heater is needed (i.e., when it is on and needs to be turned off, or when it is off and needs to be turned on).

15 Time vs. Event Triggered The FSM for the thermostat could be event triggered, like the garage counter, In which case it will react whenever a temperature input is provided. Alternatively, it could be time triggered, meaning that it reacts at regular time intervals. The definition of the FSM does not change in these two cases. It is up to the environment in which an FSM operates when it should react.

16 Actions On a transition, the action (which is the portion after the slash) specifies the resulting valuation on the output ports when a transition is taken. If q 1 and q 2 are pure outputs and q3 has type N, then the following are examples of valid actions: q 1 q 1, q 2 q 1 is present and q 2 and q 3 are absent q 1 and q 2 are both present and q 3 is absent q 3 1 q 1 and q 2 are absent and q 3 is present with value 1. q 3 1, q 1 q 1 is present, q 2 is absent, and q 3 is present with value 1. (nothing) q 1, q 2, and q 3 are all absent. Any output port that is not mentioned in a transition that is taken is implicitly absent. When assigning a value to an output port we use the notation name: = value to distinguish the assignment from a predicate, which would be written name = value. If there is only one output, then the assignment need not mention the port name.

17 When a Reaction Occurs Nothing in the definition of a state machine constrains when it reacts. The environment determines when the machine reacts. We will describe later a variety of mechanisms and give a precise meaning to terms like event triggered and time triggered. For now, however, we just focus on what the machine does when it reacts.

18 Reaction When the environment determines that a state machine should react, the inputs will have a valuation. The state machine will assign a valuation to the output ports and (possibly) change to a new state. If no guard on any transition out of the current state evaluates to true, then the machine will remain in the same state. It is possible for all inputs to be absent at a reaction. Even in this case, it may be possible for a guard to evaluate to true, in which case a transition is taken. If the input is absent and no guard on any transition out of the current state evaluates to true, then the machine will stutter. A stuttering reaction is one where the inputs and outputs are all absent and the machine does not change state. No progress is made and nothing changes.

19 Example In the counter example, if on any reaction both inputs are absent The machine will stutter. If we are in state 0 and the input down is present, then the guard on the only outgoing transition is false, and the machine remains in the same state. However, we do not call this a stuttering reaction because the inputs are not all absent.

20 Car arrival when count = 0 Our informal description of the garage counter did not explicitly state what would happen if the count was at 0 and a car departed. A major advantage of FSM models is that they define all possible behaviors. The FSM model for the garage counter defines what happens in this circumstance. The count remains at 0. As a consequence, FSM models are amenable to formal checking, which determines whether the specified behaviors are in fact desirable behaviors. The informal specification cannot be subjected to such tests, or at least, not completely.

21 Default Transitions Although it may seem that the FSM model does not define what happens if the state is 0 and down is present, it does so implicitly the state remains unchanged and no output is generated. The reaction is not shown explicitly in the diagram. Sometimes it is useful to emphasize such reactions, in which case they can be shown explicitly. A convenient way to do this is using a default transition: true / up down / 1 0 down up / 0 The default transition is denoted with dashed lines and is labeled with true /. A default transition is enabled if no non-default transition is enabled and if its guard evaluates to true. In the above figure, therefore, the default transition is enabled if up down evaluates to false, and when the default transition is taken the output is absent.

22 Default Priorities Are Syntactic Sugar Default transitions provide a convenient notation, but they are not really necessary. Syntactic Sugar: Any default transition can be replaced by an ordinary transition with an appropriately chosen guard. For example, we could use a transition with guard (up down).

23 Priorities The use of both ordinary transitions and default transitions in a diagram can be thought of as a way of assigning priority to transitions. An ordinary transition has priority over a default transition. When both have guards that evaluate to true, the ordinary transition prevails. Some formalisms for state machines support more than two levels of priority. For example SyncCharts associates with each transition an integer priority. This can make guard expressions simpler, at the expense of having to indicate priorities in the diagrams

24 Software Tools Supporting FSMs FSMs have been used in theoretical computer science and software engineering for quite some time. A number of software tools support design and analysis of FSMs: Statecharts (Harel, 1987), a notation for concurrent composition of hierarchical FSMs, has influenced many of these tools. One of the first tools supporting the Statecharts notation is STATEMATE (Harel et al., 1990), which subsequently evolved into Rhapsody and Rational Rose, sold by IBM. Many variants of Statecharts have evolved (von der Beeck,1994), and some variant is now supported by nearly every software engineering tool that provides UML (unified modeling language) capabilities (Booch et al., 1998). SyncCharts (Andre, 1996) is a particularly nice variant in that it borrows the rigorous semantics of Esterel (Berry and Gonthier, 1992) for composition of concurrent FSMs. LabVIEW supports a variant of Statecharts that can operate within dataflow diagrams MATLAB/Simulink with its Stateflow extension supports a variant that can operate within continuous-time models.

25 Mathematical Notation The graphical notation for FSMs defines a specific mathematical model of the dynamics of a state machine. A mathematical notation with the same meaning as the graphical notation sometimes proves convenient, particularly for large state machines where the graphical notation becomes cumbersome. In such a mathematical notation, a finite-state machine is a five-tuple: where States is a finite set of states Inputs is the set of input valuations States, Inputs, Outputs, update, initialstate Outputs is the set of output valuations update : States Inputs States Outputs is an update function, mapping a state and an input valuation to a next state and an output valuation; initialstate States is the initial state

26 Reactions The FSM progresses in a sequence of reactions. At each reaction, the FSM has a current state, and the reaction may transition to a next state, which will be the current state of the next reaction. We can number these states starting with 0 for the initial state. Specifically, let s: N States be a function that gives the state of an FSM at reaction n N. Initially, s(0) = initialstate. Let x: N Inputs and y: N Outputs denote that input and output valuations at each reaction. Hence, x(0) Inputs is the first input valuation and y(0) Outputs is the first output valuation. The dynamics of the state machine are given by the following equation: s n + 1, y n = update(s(n), x(n)) This gives the next state and output in terms of the current state and input. update encodes all the transitions, guards, and output specifications in an FSM. The term transition function is often used in place of update function.

27 Inputs and Output Valuations The input and output valuations also have a natural mathematical form. Suppose an FSM has input ports P = p P has a corresponding type V p. p 1,, p N, where each Then Inputs is a set of functions of the form i: P V p1 V pn absent where for each p P, i(p) V p absent gives the value of port p. Thus, a function i Inputs is a valuation of the input ports. We can define valuations for the output ports in a similar way.

28 Example: The Garage Counter The Garage Counter FSM can be mathematically represented as follows: States = 0, 1,, M Inputs = present, absent up,down Outputs = 0, 1,, M, absent count initialstate = 0 The update function is given by update s, i = for all s States and i Inputs. s + 1, s + 1 if s < M i up = present i down = absent s 1, s 1 if s > 0 i up = absent i down = present s, absent otherwise Note that an output valuation o Outputs is a function of the form o: count {0, 1,, M, absent}. The first alternative gives the output valuation as o = s + 1, which we take to mean the constant function that for all q Q = {count} yields o(q) = s + 1. When there is more than one output port we will need to be more explicit about which output value is assigned to which output port. In such cases, we can use the same notation that we use for actions in the diagrams.

29 Determinacy A state machine is said to be deterministic if, for each state, there is at most one transition enabled by each input value. The formal definition of an FSM given above ensures that it is deterministic, since update is a function, not a one-to many mapping. The graphical notation with guards on the transitions, however, has no such constraint. Such a state machine will be deterministic only if the guards leaving each state are nonoverlapping. Note that a deterministic state machine is determinate, meaning that given the same inputs it will always produce the same outputs. However, not every determinate state machine is deterministic.

30 Receptiveness A state machine is said to be receptive if, for each state, there is at least one transition possible on each input symbol. In other words, receptiveness ensures that a state machine is always ready to react to any input, and does not get stuck in any state. The formal definition of an FSM given above ensures that it is receptive, since update is a function, not a partial function. It is defined for every possible state and input value. Moreover, in our graphical notation, since we have implicit default transitions, we have ensured that all state machines specified in our graphical notation are also receptive. It follows that if a state machine is both deterministic and receptive, for every state, there is exactly one transition possible on each input value.